Fall Co-Op/Intern - Design Verification Engineer

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Cirrus Logic's Mixed Signal Audio Verification/Validation Engineering team is hiring i
nterns 
to 
assist experienced engineers with functional verification of mixed-signal audio CODECs. 
This is an opportunity to 
work closely with digital/analog designers, applications engineers and manufacturing test to support both pre-silicon verification and post silicon validation efforts.
Responsibilities
Assist with verification planning
Support with testbench development
Maintenance with failure analysis and resolution
Help with coverage analysis and population
Work on digital/mixed-signal modeling, directed/constraint-random test generation, and flow development
Required Skills & Qualifications
Must be pursuing a MSEE/MSCE
Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/UVM, Vera, e)
Preferred Skills & Qualifications 
Scripting (e.g. Perl, Python, Unix/Linux shell)
Knowledge of signal processing concepts, Matlab
Object oriented programming (e.g. SystemVerilog)
This position is located in Austin, TX
Cirrus Logic follows a 2 day in-office work schedule but interns should expect to be in the office more often, up to 5 days per week, based on business needs and team preference. Interns must be based within commutable distance of the work location listed on the job posting, or willing to relocate prior to beginning their internship with Cirrus Logic.
Cirrus Logic is an Equal Opportunity/Affirmative Action Employer. We strive to select the best qualified applicant for any opening and to reward employees based on their skills, experience and performance. We do not discriminate on the basis of race, color, national origin, pregnancy status, marital status, gender, age, religion, physical or mental disability, medical condition, veteran status, sexual orientation, gender identity, genetic information or any other characteristic protected by law.
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